`include "../define.svh"
module mult_out (
    input clk,
    input sys_rst_n,
    input [7:0]e_final,
    input [23:0]m_final,
    input [1:0]data_type,
    input s_final,
    input spec_valid,
    input [22:0]m_spec_in,
    input [7:0]e_spec_in,
    //input s_spec_in,
    output reg [31:0]product_o_reg
);
    wire [31:0] mult_out;
    wire [31:0] mult_out_spec;
    wire [31:0] product_o;

    assign mult_out=(data_type==`FP16) ? {16'd0,s_final,e_final[4:0],m_final[9:0]}:{s_final,e_final[7:0],m_final[22:0]};  //组合常规路径结果

    assign mult_out_spec=(data_type==`FP16) ? {16'd0,s_final,e_spec_in[4:0],m_spec_in[9:0]}:{s_final,e_spec_in[7:0],m_spec_in[22:0]};  //组合特殊路径结果

    assign product_o=spec_valid ? mult_out_spec : mult_out;
     always @(posedge clk or negedge sys_rst_n) begin
        if (!sys_rst_n) begin
            product_o_reg<=32'd0;
        end
        else product_o_reg<=product_o;
    end 
    //assign product_o_reg = product_o;
endmodule